{"created":"2023-05-15T14:41:40.559917+00:00","id":1632,"links":{},"metadata":{"_buckets":{"deposit":"0bfc2632-f746-490a-9ce9-0346bee1ae83"},"_deposit":{"created_by":3,"id":"1632","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"1632"},"status":"published"},"_oai":{"id":"oai:ksu.repo.nii.ac.jp:00001632","sets":["14:13:67"]},"author_link":["4160","20907"],"control_number":"1632","item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2013-03","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"70","bibliographicPageStart":"63","bibliographicVolumeNumber":"42","bibliographic_titles":[{"bibliographic_title":"京都産業大学論集. 自然科学系列"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"大規模論理回路の設計検証やテスト生成において,大規模組み合わせ論理回路の論理シミュ レーションが必要となる.これを高速化するために,数百の演算ユニット(コア)を利用でき るGPGPU技術を用いて大量の入力パタンを並列に処理する論理シミュレーション手法を提案する.ISCASのベンチマーク回路の論理シミュレーションで提案手法により約12~18倍高速化することができた.","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"京都産業大学"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11923897","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1348-3323","subitem_source_identifier_type":"PISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"森, 裕紀","creatorNameLang":"ja"},{"creatorName":"MORI, Hiroki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"平石, 裕実","creatorNameLang":"ja"},{"creatorName":"HIRAISHI, Hiromi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-09-30"}],"displaytype":"detail","filename":"AHSUSK_NSS_42_63.pdf","filesize":[{"value":"334.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"AHSUSK_NSS_42_63.pdf","url":"https://ksu.repo.nii.ac.jp/record/1632/files/AHSUSK_NSS_42_63.pdf"},"version_id":"53f5e25b-6450-4a9b-9a71-120e9550c6f0"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"GPGPU","subitem_subject_scheme":"Other"},{"subitem_subject":"論理シミュレーション","subitem_subject_scheme":"Other"},{"subitem_subject":"組み合わせ論理回路","subitem_subject_scheme":"Other"},{"subitem_subject":"並列処理","subitem_subject_scheme":"Other"},{"subitem_subject":"論理設計","subitem_subject_scheme":"Other"},{"subitem_subject":"GP-GPU","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Logic Simulation","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Combinatorial Circuits","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Parallel Processing","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Logic Design","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"GPGPUによる組み合わせ論理回路の入力パタン並列論理シミュレーション","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"GPGPUによる組み合わせ論理回路の入力パタン並列論理シミュレーション","subitem_title_language":"ja"},{"subitem_title":"Input Pattern Parallel Logic Simulation of Combinatorial Circuits Using GP-GPU","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"3","path":["67"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2017-09-30"},"publish_date":"2017-09-30","publish_status":"0","recid":"1632","relation_version_is_last":true,"title":["GPGPUによる組み合わせ論理回路の入力パタン並列論理シミュレーション"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-08-09T06:19:32.192217+00:00"}